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System Identification

Process with regulator optimization

Evaluate regulator performance & push to FGC

Measure performances

Set / Choose closed loop system -goal- performance

Choose / Set I.reg.rate speed vs I.closed.loop		Choose your reg.i.iteration (RST refresh algorithm) rate: reg.i.period_iters. Default i.loop.bandwidth = 1/14 x 1/(100us x reg.i.period_iters), depending on converter bandwidth & load type. - Fast pulsed: reg.i.period_iter = 1;2 - Std pulsed: reg.i.period_iter = 5;10 - DC: reg.i.period_iter = 10;20

System identification

Set your converter at current of interest		Converter can be set in V or I reg.mode, before PRBS or Sinefit identification, both performed in voltage mode.
Launch Fresco, select your device & open PRBS Tab		Identify the system being controlled by the FGC: Imeas=f(Vref), including load and converter, using PRBS and correct period iteration = reg.i.period_iters. It is only required to identify the system where the closed loop is expected (no need to get all low freq. poles). Period iteration is limited to 10. For a reg.i.period_iter of 20 or more, use Period iterations = 10. The regulator synthesis will adjust the phase automatically.
Impact of period.div on system identification		Data driven step which follows relies on discrete system being evaluated. If the gain is unchanged, phase includes the delay from system discretisation. It is then required to use the correct period iteration number included in the data being proposed to the automatic optimization.

Process with regulator optimization

Set corrector parameters in Data Driven Tab		- Verify reg.i.period_iters is correct (refresh page). - Keep proposed bandwidth. - Indicate 2 integrators to reduce tracking error. - Set modulus margin to 0.8 (increases stability, especially for DC loads).
Choose Input Data (System Model)		Choose or FortLogs input data, and select the adequate acquisition in the proposed list or your own built model file (.csv). Then lauch RST & ILC optimization.
Optimize input data for regulator synthesis		If the regulator synthesis fail, or step response shows a slow recovering static error for pulsed loads, decrease the modulus margin to 0.7, 0.6 and 0.5 (not below 0.5!). If the regulator still fails, start again from "Set / Choose closed loop system -goal- performance" with a higher reg.i.period_iter.

Evaluate regulator performance & push to FGC

Appreciate the result obtained by optimization process		Some given parametric data allows to judge if obtained regulator is suitable or not. Push corrector to the FGC if achieved performances seems close to initial desired closed i.loop ones.
Get a better idea of corrector robustness.		It is possible to get a good idea of the "corrector" viability. A smooth Nyquist plot is a key point for stable result.

Measuring real system performances

Use PowerSpy		User PowerSpy to measure performance, directly on signals of interest I_MEAS_REG & I_REF_USER, found in I_REF_MPX Powerspy logs, and using error signal as well I_ERR_(A).
		To select them, if not shown per default, please choose I_REF_MPX channel.
		Open selection pane.
		Fetch signals and replace them.
Use FGCRun+		- g meas.i.max_abs_err zero. - s ref sine,App,nb,per. or - s ref square,Astep,nb,per. - s ref.run - g meas.i.max_abs_err.